The growth of wearables and near-field applications has led to the design of wireless solutions that are more efficient and give designers the opportunity to integrate with SoCs through the integration of wireless capabilities such as Bluetooth Low Energy PHY and Link Layer IP, Thus reducing IoT SoC cost and power consumption ... Bluetooth, Wi-Fi, LTE and 5G technologies make wireless connectivity widely available. While each technology has its own unique capabilities and benefits, designers must decide whether to integrate them in a single chip or use an external wireless chip solution. The advantages of IoT applications integrating wireless capabilities are becoming increasingly significant, especially when designing toward more advanced processes. Currently, Bluetooth technology with low power consumption is becoming the standard choice for wearable devices and object tracking or "smart" IoT applications. The Bluetooth 5 standard is expected to enter smart home applications with broader reach, faster speeds and the ability to go beyond point-to-point communications. According to a recent user survey by Synopsys, the IoT SoC design from 2013 to 2015 has seen substantial growth, benefiting from the new wearable device IC market contribution. In addition, according to Teardown.com, the number of wireless chips in more than 800 mobile and wearable products it disassembled between 2012 and 2015 exceeded the actual number of products, indicating that in some designs multiple wireless IC. Based on these reports, the growth of wearable devices and smart hardware applications has driven the design of add-on wireless solutions and created the opportunity for designers to reduce the cost and power consumption of IoT SoCs through the integration of wireless capabilities. This article describes the benefits of integrating wireless technologies such as Bluetooth Low Energy in a single-chip SoC to create a complete solution for low-power Bluetooth physical layer (PHY) and link-layer IP. Wireless system architecture In the past few years, a variety of wireless technology solutions have emerged (Figure 1): ? Standalone RF Transceiver: In this legacy setup, the transceiver chip contains the controller and PHY, or link layer and PHY (in the case of Bluetooth). The transceiver chip connects to the main SoC, which contains the software stack and application code. Wireless Network Processor: This build uses a dedicated processor with an integrated wireless protocol stack to bring more value to the wireless chipset and let the main SoC focus resources on the application. Fully Integrated Wireless SoC: This is a single-chip, single-build solution for specific wireless technologies, especially Bluetooth Low Energy for IoT applications. The link layer and PHY are integrated into the SoC to execute all software stacks and application code. Wireless Portfolio Chipset Solution: The traditional architecture for mobile applications combines several wireless technologies such as Wi-Fi and Bluetooth, transceivers and connected to SoCs containing digital modem chips in a single transceiver. All software, wireless stack and application code are located in external, non-volatile memory. 20170320 Synopsys TA31P1 Figure 1: Bluetooth Chipset Options (source: ti.com) Process technology plays a key role in deciding which solution to create the best for the target application. Stand-alone RF transceivers use traditional nodes such as 180nm. For wireless network processors, wireless protocol stacks are embedded in RF transceivers, often using mature 90nm nodes. Nodes that use 40nm and 55nm technologies in an integrated wireless solution are gaining popularity due to the combination of available embedded flash and mixed-signal IP, including wireless IP. This similar overall wireless SoC solution is expected to be commonly used 28nm node. Among them, the protocol stack, RF transceiver and application code are integrated in a single SoC. For mobile applications processors, the combo chip (Combo) solution is still popular architecture, it can use the most advanced technology for chip area and cost optimization. With unrestricted off-chip memory, these systems provide additional resources for programmers, but the system will have as many as three total chips in the system and one or two in the other three. This clearly shows the benefits wireless converges when the process nodes are able to effectively collocate available IP solutions and this is why the fully integrated wireless SoC system architecture has become commonplace. Industrial application case For the current wearable design, a fitness bracelet that wirelessly connects with Bluetooth Low Energy only includes a SoC connected to an external, low-power Bluetooth IC via a UART or I2C bus. Similarly, virtual reality (VR) glasses communicate with the game controller using a standard Bluetooth wireless network processor. External low-power Bluetooth chipsets can also be found in smart home products such as door locks, lighting and indoor location beacons. These examples show the opportunity to integrate wireless capabilities into the system SoCs for more cost savings. If the design also includes higher bandwidth wireless technologies such as Wi-Fi, wireless combo chip solutions that incorporate multiple wireless technologies, processors, and external memory are available. For example, augmented reality (AR) glasses require higher processing power, so designers must upgrade similar mobile platform designs. Wireless capabilities are replacing many of the traditionally online features. Especially low-power Bluetooth, which is used to diagnose and transmit low-bandwidth information, while UARTs, I2C, SPI, and USB were traditionally used. The benefits of integrating wireless technology in SoCs Now that we have seen the opportunity to integrate wireless capabilities in a single SoC, let's talk about its advantages and disadvantages. Wireless network processors, such as standalone low-power Bluetooth solutions, continue to be used in the certification system, simplifying the design of the module certification process. These standalone low-power Bluetooth solutions not only simplify the certification process, but also provide reliable connectivity and common system design methods related to components such as antennas. Integral solutions provide additional benefits, including low power consumption, low cost, low latency, and small footprint, driving the market to adopt and design fully monolithic wireless SoCs. Compared to using the SPI bus, the data streamed through the AMBA AHB can reduce latency by 5 to 10 cycles, lengthening idle time and saving power. In fact, in the recently released Microsoft Wireless Power Study, "the dominating parameter in power consumption is not the active or standby current but the time it takes to reconnect after the sleep cycle has ended And the degree to which the RF module is asleep. " In addition to power and latency improvements, the wireless consolidation solution removes the complete chipset, reduces packaging costs, and reduces the extra pin and power management IP required. This will reduce packaging costs by more than $ 0.15 and reduce the number of pins used to connect more wireless network processors by 20-30. These savings, coupled with the removal of duplicate power management components, reduce PCB area and make overall system cost reduction more attractive.